Method of forming high voltage n-ldmos transistors having shallow trench isolation region with drain extensions

ABSTRACT

A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No.10/991,936 filed on Nov. 18, 2004 which is a divisional of U.S. patentapplication Ser. No. 10/249,766, filed on May 6, 2003, which is now U.S.Pat. No. 6,876,035, which are both fully incorporated herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to transistors and moreparticularly to an improved N-type lateral double diffusion metal oxidesemiconductor that has a shallow trench isolation region between thegate and the drain.

2. Description of the Related Art

Power semiconductor devices are currently being used in manyapplications. Such power devices include high-voltage integratedcircuits, which typically include one or more high-voltage transistors,often on the same chip as low-voltage circuitry. A commonly usedhigh-voltage component for these circuits is the lateral double diffusedMOS transistor (LDMOS). LDMOS structures used in high-voltage integratedcircuits may generally be fabricated using some of the same techniquesused to fabricate the low voltage circuitry or logic circuitry. Ingeneral, these existing LDMOS structures are fabricated in a thickepitaxial layer of opposite conductivity type to the substrate or theyuse a thin epitaxial layer and apply the RESURF (reduced surface field)principle (e.g., see U.S. Pat. No. 6,242,787, that is incorporatedherein by reference, for a complete description of RESURF) to equallydistribute the applied drain voltage laterally across the siliconsurface in the drift region of the device.

High-power applications call for the use of such lateral double diffusedMOS transistors primarily because they possess lower “on” resistance(“Rdson”), faster switching speed, and lower gate drive powerdissipation than their bi-polar counterparts. These devices haveheretofore also been strongly associated with bi-polar based processflows when integrated into a Bi-CMOS (bipolar complementary metal oxidesemiconductor) environment.

SUMMARY OF THE INVENTION

The invention provides a transistor having a gate, a channel regionbelow the gate, a source region on one side of the channel region, adrain region on an opposite side of the channel region from the sourceregion, a shallow trench isolation (STI) region in the substrate betweenthe drain region and the channel region, and a drain extension below theSTI region. The drain extension is positioned along the bottom of theSTI region and along the portion of sides of the STI. Portions of thedrain extension along the bottom of the STI may comprise differentdopant implants than the portions of the drain extensions along thesides of the STI. Portions of the drain extensions along sides of theSTI extend from the bottom of the STI to a position partially up thesides of the STI. The STI region is below a portion of the gate. Thedrain extension provides a conductive path between the drain region andthe channel region around a lower perimeter of the STI. The drain regionis positioned further from the gate than the source region.

The invention also discloses a method of manufacturing a transistor.First, the method forms a trench in a substrate. Next, the methodpartially fills the trench with a sacrificial material, and then formsspacers in the trench above the sacrificial material.

The method removes the sacrificial material and implants a drainextension through the trench into exposed portions of the substrate. Thedrain extension is implanted to regions of the substrate along sides andthe bottom of the trench. The method fills the trench with a shallowtrench isolation (STI) material. The method defines a channel region inthe substrate on one side the STI material. The invention forms a sourceregion in the substrate on an opposite side of the channel region fromthe STI material. The method then forms a drain region in the substrateon an opposite side of the STI material from the channel region. Lastly,the method forms a gate above the channel region.

The implanting process includes a vertical implant which forms a drainextension in the portion of the substrate along the bottom of thesubstrate and an angled implant to form the drain extension in theportion of the substrate along the sides of the substrate.

The spacers and the sacrificial material control the size and locationof the drain extension. The implanting process forms portions of thedrain extensions along sides of the STI from the bottom of the STI to aposition partially up the sides of the STI. The forming of the gateextends a portion of the gate over the STI material. The drain extensionprovides a conductive path between the drain region and the channelregion around a lower perimeter of the STI. The process of forming thedrain region positions the drain region further from the gate than thesource region. The process of implanting the drain extension includesprotecting regions other than the trench to limit the implanting processto the trench.

The manufacturing process shown above is advantageous when compared toconventional manufacturing processes because the invention forms thedrain extension directly through the trench opening. Thus, a lowerenergy implant can be used than is used conventionally. Further, thepenetration depth and unwanted diffusion is easily controlled becausethe implant is being made through the trench opening. In addition, thetrench opening aligns the impurity implant more precisely thanconventional methods that must pass the higher energy implant throughthe recessed oxide. Therefore, as shown above, the invention providesimproved channel length control with maskless trench aligned implant andreduced straggle (unwanted diffusion) of the deep implant. This reduceson resistance (Rdson), and overlap capacitance (Cov), and increases theon current (Ion).

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood from the following detaileddescription of a preferred embodiment(s) of the invention with referenceto the drawings, in which:

FIG. 1 is a schematic diagram of a LDMOS;

FIG. 2 is a schematic diagram of a LDMOS;

FIG. 3 is a chart showing the performance of a LDMOS;

FIG. 4 is a schematic diagram of a LDMOS;

FIG. 5 is a schematic diagram of a partially completed LDMOS;

FIG. 6 is a schematic diagram of a partially completed LDMOS;

FIG. 7 is a schematic diagram of a partially completed LDMOS;

FIG. 8 is a schematic diagram of a partially completed LDMOS;

FIG. 9 is a schematic diagram of a partially completed LDMOS;

FIG. 10 is a schematic diagram of a partially completed LDMOS; and

FIG. 11 is a flowchart illustrating the embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Integration of microelectronics into consumer appliances, automotive,space technologies, etc., drives a market utilizing high performanceCMOS (complementary metal oxide semiconductor), BJT's (bipolar junctiontransistors) and power MOS (metal oxide semiconductor) drivers. Thelateral DMOS (LDMOS) transistor is typically chosen as the drivingtransistor, capable of switching high voltages.

FIG. 1 illustrates a typical N-DMOS device schematic. The deviceincludes a substrate 10, source 11, gate 12, and drain 13. In the deviceoff state, the voltage of the drain 13 (Vdrain) is typically at a highpositive potential (i.e., the “appliance switching or mixed level”). Thevoltage of the gate 12 (Vgate) is typically at or near ground, i.e.,less than the turn on potential of the device. The voltage differentialthat will exist between the drain and gate presents significant stressupon the gate oxide and it is an important design goal to protect thegate oxide from being destroyed by these large voltages. The voltage ofthe source 11 (Vsource) may be at ground, or at the CMOS internal level,and for sake of simplicity, the voltage of the substrate 10 (Vsubstrate)is at ground also. In the on state, the Vdrain to source is typically athundreds of millivolts, and the Vgate to source voltage is at the CMOSinternal level. A typical N-LDMOS threshold voltage is approximately 1volt. Thus, in the preferred on-state Vgs>>Vt, and Vds<<(Vgs−Vt), thusthe device operates in a linear mode. Vdrain, or the external appliancepotential can approach voltage levels in excess of 20 volts, while theinternal CMOS levels are typically between 1 volt and 3.3 volts.Internally, the CMOS levels cannot operate at the appliance voltagelevels, as gate oxides would be destroyed, and the appliance voltagescannot operate at the internal CMOS levels, as the voltages are too lowfor appliance operation.

FIG. 2 displays a cross-section of a 24 volt N-LDMOS device. Some of theelements illustrated in FIG. 2 include the n buried layer 200, the body216, a combined source/body contact 214 (p− doped and n+ doped regions220, 222, and n+ extension 232), a sidewall spacer 224, and apolysilicon gate 212. Item 218 superimposes the parasitic NPN schematicover the structure. The drain 208 includes n+ region 206. The extendeddrain region, comprising an n-drift region 202 and an n-layer 204,extends under a field oxide 210 for on-resistance (Rdson) control. Thepolysilicon gate 212 extends over the field oxide 210 and a gate oxide213 is below the gate 212. To minimize device area the p-body and sourceterminals are usually common 214 but for substrate current analysis,device arrays can also be fabricated with separate source and bodycontacts. The threshold voltage (Vt) for this device is ˜1.0 V.

The performance parameters for an optimized design are low andcontrolled Rdson/Overlap Capacitance at the drain terminal, and highVdrain breakdown voltage. This implies that a “high” drive current isthe result of a minimized and controlled Rdson for the LDMOS device. InFIG. 2, one practice of designing the high voltage drain 208 uses aphoto-resist mask 226 over the grown thick oxide. The n− deep part 204of the junction is implanted 228 through the photo-resist 226, and theshallow n+ part 206 of the junction follows 228. This process results ina device having a large straggle in the control of the lateral extentdue primarily to the large implant energy (e.g., 80 Kev) required toreach through the recessed oxide and the mask alignment to the recessedoxide.

The limitations described above also limit the minimum channel lengthdesign for such a device, further constraining the chip function due toI/O requirements. More specifically, the channel region 230 runsapproximately between the n− layer 204 and the n+ doped region 222. Thesize and shape of the bird's beak of the field oxide 210 (e.g., the leftand right sides of the field oxide 210 in FIG. 2) restricts the lengthof the channel region 230 and is a very difficult feature to control.Thus, the bird's beak shown in FIG. 2 substantially limits the controlover channel length. Device layout has a substantial impact on LDMOS HCperformance. FIG. 3 is taken from D. Brisbon et al., “Hot CarrierReliability and Design of N-LDMOS Transistor Arrays” 2001 IRW FinalReport (incorporated herein by reference) and displays measured Rdsonlifetime as a function of specific on-resistance (Rdson_sp) and sourceto drain edge spacing L, where: Rdson_sp=Rdson*Area Array. FIG. 3 showsthat increasing L by just 0.9 μm increases Rdson HC lifetime by sevenorders of magnitude, though this improved HC performance is attained atthe expense of increased Rdson_sp and array area. Therefore, control ofthe channel length (e.g., source to drain spacing) is crucial to deviceperformance and longevity. In addition, lack of control of the L-DMOShigh voltage junction leads to hot carrier reliability issues thatparallel spacer-induced damage in CMOS.

The invention provides control over the source to drain spacing byintegrating shallow trench isolation (STI) and low energy pre-implantsprior to isolating adjacent transistors. The pre-implant is performed todope the drain extension. One additional control feature provided by theinvention is a STI sidewall spacer formation that is used to control theout-diffusion of the self-aligned junction floor pre-implant.

FIG. 4 illustrates this self-aligned junction floor n− implant 40 belowthe shallow trench isolation 41 that is added to the conventionalstructure for control of both source to drain spacing and Rdson. Theimplant 40 replaces the conventional drain extension and comprises thedrain extension in the inventive structure. In addition, in a secondembodiment (discussed in greater detail below with respect to FIGS. 9and 10), the invention provides vertical drain extensions 42 on the sidewalls of the STI 41. With the vertical drain extensions 42, theparasitic device resistance is easily controlled. A continuousconductive path is supplied around the periphery of the shallow trenchisolation 41 from the drain 206, 204 directly to the channel region 230.In addition, the formation of the trench structure 41 eliminates the“birds beak” field oxide 210 shape and thereby avoids all disadvantagesassociated with a birds beak structure, such as difficulty incontrolling channel length, Vdrain degradation, etc.

The structure shown in FIG. 4 benefits from a number of advantages whencompared to the structure shown FIG. 2 because the high voltage drain206 is thoroughly insulated from the gate 212 (and underlying sensitivegate oxide 213) by the shallow trench isolation region 41. Since the STItrench is the first element in this process, it is easily aligned with(e.g., self-aligned) with the later formed CMOS device. To the contrary,in FIG. 2, the field oxide 210 encroaches upon the CMOS gate.

FIGS. 5-8 show one embodiment where the deep drain implant is controlledby using a low energy STI trench. In this embodiment, the shallow trenchisolation region 41 is formed before the remaining structures of thetransistor are formed. Therefore, such structures are not illustrated inthe drawings. However, one ordinarily skilled in the art wouldunderstand that the shallow trench isolation region 41 and drainextension 40 could easily be formed at many different processing pointsduring the creation of the transistor, and the embodiments describedherein are intended to cover all such possible methodologies.

Turning to FIG. 5, the invention begins with a substrate 50 (e.g.,silicon, pre-doped or undoped) with an overlying dielectric pad 51formed according to well known processes. In FIG. 6, a mask 60 (such asa photolithographic mask) is formed over the pad material 51 andpatterned to create an opening 62. An etching process is then performedto remove the exposed portions of the pad material 51 and the silicon 50to create a trench 61 in the silicon 50.

The mask 60 is then removed, as shown in FIG. 7. Sidewall spacers 71(e.g., nitride, oxide, etc.) are then formed in the trench 61. Theprocesses for forming sidewall spacers are well known to thoseordinarily skilled in the art. For example, one process deposits orgrows the spacer material and then performs a directional etch thatremoves material from horizontal surfaces at a higher rate than itremoves material from vertical surfaces, thereby leaving the spacersonly on the sidewalls of the structure. Any such processes could be usedto form the sidewall spacers 71. An implant (e.g., n-implant) 70 is thenperformed to create the impurity implantation region 72. By directlyimplanting into the silicon 50, a lower energy and more highlycontrolled implant can be utilized. Further, the size of the spacers 71can be varied to provide precise control regarding the size of theimpurity region 72.

In FIG. 8, the opening 61 is filled with insulating shallow trenchisolation material 40 (e.g., nitride, oxide, etc.) and a thermalannealing process is performed on the structure to diffuse the impurityimplantation region 72 outward to create the junction outdiffusionregion 81. After this, conventional processing such as that described inU.S. Pat. No. 6,242,787 (incorporated herein are reference) is performedto create the drain region, source, gate, insulators, contacts, etc.that form the final functional device shown in FIG. 4. The STI region 41can comprise a portion of the gate oxide 213 in the final structure.

FIGS. 9 and 10 illustrate a second embodiment where the deep drainimplant is controlled by utilizing an angled implant method. Morespecifically, the structure shown in FIG. 9 is similar to the structureshown in FIG. 7, except that in FIG. 9, before the sidewall spacers 71are formed, an oxide fill 90 is grown in the lower portion of the trench61. Then, as shown in FIG. 10, the oxide film 90 is removed and thevertical implant 70 is performed. In addition one or more angledimplants 100 (with the same or different impurities, concentrations,etc.) are performed to implant impurities 42 along one or both of theexposed sidewalls of the trench that are below the spacers 71. The depthat which the oxide fill 90 is grown determines the height of the exposedportion below the spacers 71 and correspondingly determines how far upthe trench sidewall from the bottom of the trench the sidewall impurityregions 42 will extend. While the sidewall impurity regions 42 are shownas extending approximately halfway up the trench sidewalls, theirposition can be controlled (by the depth of the oxide fill 90) dependingupon the individual circuit designer's requirements. Next, the trench isfilled with the STI material and the remaining device structures areformed as was done in FIG. 8.

FIG. 11 is a flow chart illustrating one embodiment of the invention. Initem 1100, the invention forms a trench in a substrate. Next, in item1102, the invention partially fills the trench with a sacrificialmaterial. The invention then forms spacers in the trench above thesacrificial material in item 1104. In item 1106, the invention removesthe sacrificial material. Next, in item 1108, the invention performs avertical implants. In item 1110, the invention performs an angledimplant. In item 1112, the invention fills the trench with a shallowtrench isolation (STI) material. In item 1114, the invention defines achannel region. In item 1116, the invention forms a source region. Initem 1118, the invention forms a drain region. In item 1120, theinvention forms a gate.

The manufacturing process shown above is advantageous when compared toconventional manufacturing processes because the invention forms thedrain extension 40, 42 directly through the trench opening 61. Thus, alower energy implant (e.g., 10-40 Kev) can be used. This is asubstantial improvement over the implants required through the Fox (210in FIG. 1). Fox implants are typically in excess of 80 Kev, and as suchthey have a very large lateral straggle, and suffer high implant damage.The high straggle effects the control of Lmin, and the implant damagecauses high device junction leakage. Further, the penetration depth andunwanted diffusion by using the trench process is easily controlledbecause the implant is made through the trench opening. In addition, thetrench opening 61 aligns the impurity implant more precisely thanconventional methods that must pass the higher energy implant throughthe recessed oxide 210. Therefore, as shown above, the inventionprovides improved channel length control with maskless trench alignedimplant and reduced straggle (unwanted diffusion) of the deep implant.This reduces on resistance (Rdson), and overlap capacitance (Cov), andincreases the on current (Ion).

While the invention has been described in terms of preferredembodiments, those skilled in the art will recognize that the inventioncan be practiced with modification within the spirit and scope of theappended claims.

1. A transistor comprising: a gate on a substrate; a channel region insaid substrate below said gate; a source region in said substrate on oneside of said channel region, a drain region in said substrate on anopposite side of said channel region from said source region; a shallowtrench isolation (STI) region in said substrate between said drainregion and said channel region, wherein said STI region comprises atrench in said substrate, sidewall spacers along walls of said trench,and an isolation material between said spacers filling said trench; anda drain extension below said STI region.
 2. The transistor in claim 1,wherein said drain extension is positioned along a bottom of said STIregion and along a portion of sides of said STI.
 3. The transistor inclaim 2, wherein portions of said drain extension along said bottom ofsaid STI comprise different dopant implants that said portions of saiddrain extensions along said sides of said STI.
 4. The transistor inclaim 2, wherein portions of said drain extensions along sides of saidSTI extend from said bottom of said STI to a position partially up saidsides of said STI.
 5. The transistor in claim 1, wherein said STI regionis below a portion of said gate.
 6. The transistor in claim 1, whereinsaid drain extension provides a conductive path between said drainregion and said channel region around a lower perimeter of said STI. 7.The transistor in claim 1, wherein said drain region is positionedfurther from said gate than said source region.
 8. The transistor inclaim 1, further comprising a gate oxide below said gate, wherein saidSTI region forms a portion of said gate oxide.